TSMC’s patented, fine-pitch copper bump-based packaging technology is used in Altera’s 20 nm Arria10 FPGAs and SoCs.
Fine-pitch copper bumps are expected to offer better quality and reliability than standard copper bumping solutions. Altera also says the package provides excellent bump joint fatigue life, improved performance in electro-migration current and low stress on the ELK (Extra Low-K) layers.
Altera is shipping Arria 10 FPGAs based on TSMC 20SoC process technology and featuring this innovative packaging technology.
Altera states in its release "TSMC’s copper bump-based package technology is scalable and ideal for products that feature large die size and small bump pitch. It includes a DFM/DFR implementation from TSMC that adjusts package design and structure for wider assembly process windows and higher reliability. The technology has demonstrated better than 99.8% production-level assembly yields."