analysis of Complex amplifier circuits
Amplifiers in cascode Configuration and their variations
are generally used to overcome Miller Capacitance, improve
the small signal gain and output impedance. Increasing number
of transistors in cascode stages result in larger small
signal gain. However the small signal analysis also gets
tedious as the number of transistors in the cascode configuration
For example let us consider a circuit as shown below. The
Cascode Load stage increase the output impedance.
The small signal equivalent circuit for the above configuration
is given below:
Now how to go ahead with the analysis of this circuit to
obtain the Small Signal Gain. Going by traditional ways
of applying KVL and KCL to analyze will consume lot of time
and also you end up getting some complex solution which
is tough to know if the result is correct. But many a time
we are not interested in such accurate results the reason
being the main aim of circuit analysis is to see how the
circuit behaves. Software simulations which are based on
complex algorithms will help to get the accurate results.
To make my point clear consider simple circuit consisting
of two parallel resistors and an input source. When we analyze
this circuit we are not including parasitic inductance and
capacitance to analyze the problem since we are not interested
such a detailed analysis. However when we run the simulation
the model file and the simulation algorithm will take care
of these issues to get you the best possible results.
Keeping this in mind we see that when we analyze this particular
amplifier circuit by traditional means we get some complex
expression and many terms end up being redundant.
So I describe below simple procedure to obtain solution
to this particular circuit in hand. If we replace the bottom
NMOS with input source by its small signal equivalent we
are reduced to following circuit. We note that in small
signal analysis the DC bias sources are replaced by short
Now there are two branches where current gmnvin can flow.
Some part of the current may through ron and remaining into
the source of transistor M2.But what we know from the basic
understanding of MOSFET is that the impedance looking into
the source of NMOS is 1/gm which is very small. So we can
see that almost all gmnvin flows into source of M2. Now
to obtain the impedance seen at the drain of M2, looking
into the drain of M2 we note that the resistance ron appear
as degenerate resistor at the source of M2.Hence the circuits
reduces to one shown below.
To proceed further with the analysis we note that M3 is
a PMOS. Again there are two branches for current to flow.
But the impedance looking into drain of M3 is rop which
is very small compared to (gmn+gmbn)ron2. Hence we can assume
that entire current flows into M3.With these assumptions
we are reduced to following circuit.
Now looking into the PMOS branch we see that M5is just a
resistor in small signal model as shown above. Now M5 appear
as degenerate resistor at the source of M5. Hence the overall
small signal equivalent circuit reduces to one below
Now it is very simple to obtain the gain and is given by
the expression below.