InGaAs FinFET devices built on CMOS silicon
Imec has announced successful replacement of silicon fins of a CMOS finFET transistor with compound semiconductor material InGaAs fins, so that compound semiconductor (III-V) material based finFETs can be fabricated on a silicon wafer. This achievement helps in volume manufacturability of a chip integrated with both CMOS silicon as well as compound semiconductor material based circuit. By using this process, both RF and logic functions can be integrated in a single monolithic chip, and also can be featured with opto-electronics interface to achieve high-speed data communication both for inter-chip as well as intra chip communication.
Imec says this achievement leads to manufacturing of high volume heterogeneous CMOS SOC on a 450 MM wafer size. This technology enables manufacturing of hybrid CMOS-RF and CMOS optoelectronics devices at nodes down to 7 nm.
This looks like a process where silicon fins were first removed by using some chemical process and then the compound semiconductor is deposited using some advanced atomic deposition process. Imec said its researchers have selectively replaced silicon fins with indium gallium arsenide (InGaAs) and indium phospide (InP), accommodating close to eight percent of atomic lattice mismatch. Imec has used techniques such as aspect-ratio trapping of crystal defects, trench structure, and epitaxial process innovations in achieving this breakthrough. Imec claims the resulting III-V device integrated on silicon FinFET device shows an excellent performance.
Leading semiconductor companies and foundries such as Intel, Samsung, TSMC, Globalfoundries, Micron, SK Hynix, Toshiba, Panasonic, Sony, Qualcomm, Altera, Fujitsu, nVidia, and Xilinx are partnering with Imec in its research project.
“To our knowledge, this is the world’s first functioning CMOS compatible III-V FinFET device processed on 300mm wafers,” stated An Steegen, senior vice president core CMOS at imec. “This is an exciting accomplishment, demonstrating the technology as a viable next-generation alternative for the current state-of-the-art Si-based FinFET technology in high volume production.”
Aaron Thean, director of the logic R&D at imec commented: “During the last decade, transistor scaling has been marked by several leaps in process technologies to provide performance and power improvements. The replacement of poly-silicon gate by high-k metal-gate in 45nm CMOS technology in 2007 represented a major inflection in new material integration for the transistor. The ability to combine scaled non-silicon and silicon devices might be the next dramatic transistor face-lift, breaking almost 50 years of all-silicon reign over digital CMOS. This work represents an important enabling step towards this new paradigm.”
With all these improvements in chip manufacturing process, one wonders is the cost of the semiconductor chip fab coming down.