VLSI design webinar on Open Source - VHDL Verification Methodology
EDA VLSI design software vendor Aldec has announced a webinar on Thursday, July 18, 201 Time: 3:00 PM - 4:00 PM CEST, presented by Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OS-VVM Chief Architect.
The abstract of the webinar is: At the lowest level, Open Source - VHDL Verification Methodology (OS-VVM), is a set of packages that provide concise and powerful methods to implement functional coverage and randomization. OS-VVM uses these packages to create an intelligent testbench methodology that allows mixing of "Intelligent Coverage" with directed, algorithmic, file based, or constrained random test approaches. Having an intelligent testbench approach built into the coverage modeling puts OS-VVM a step ahead of other verification methodologies, such as SystemVerilog and UVM.
Aldec suggest VLSI chip design engineers to attend the webinar titled "VHDL Intelligent Coverage using Open Source - VHDL Verification Methodology (OS-VVM)" and learn how to utilize OS-VVM to add functional coverage, Intelligent Coverage, and constrained random methods to your current testbench.
Benefits of OS-VVM as said by Aldec includes:
Faster Test Construction, focus is on functional coverage
Faster simulations: O(Log N) faster than constrained random and no solver.
Goes beyond other verification languages (SystemVerilog and 'e')
Works with your current VHDL testbench
Uses entity and architectures for structure (just like RTL).
Is language accessible. Able to refine with code.
Readable by ALL (Verification and RTL engineers).
OS-VVM is open-source package based. It compiles under VHDL-2008 or VHDL-2002 (with minor adaptations). More can be found at www.osvvm.org
To know more on this webinar visit: http://www.aldec.com/en/events/303
To register for this webinar visit: http://www.aldec.com/en/events/register/303