Synopsys new 2.5 Gbps MIPI IP consumes lesser space and power
Date: 17/09/2014
Synopsys said it has cut the area and power consumption of its DesignWare MIPI D-PHY by 50 percent compared to competitive solutions while increasing performance to 2.5 Gbps per lane.
MIPI D-PHY v1.2 specification compliant DesignWare MIPI D-PHY is the physical layer used for MIPI CSI-2 and DSI Host and Device applications to connect image sensors and displays to SoCs in mobile and embedded applications. For high-resolution output, four lanes of the DesignWare MIPI D-PHY can be aggregated to support 10 Gbps speeds and eight data lanes can be aggregated to achieve 20 Gbps speeds.
"The DesignWare MIPI D-PHY offered low power consumption, high performance and configurability options that were critical to the success of our Myriad 2 Vision Processing Unit," said Sean Mitchell, senior vice president and COO at Movidius. "Using Synopsys' high-quality MIPI IP solutions that support the latest specifications and features helps us quickly incorporate needed functionality into our SoCs with less risk."
"To accelerate their time-to-market, designers of high-resolution products require proven IP that helps lower the risk of incorporating the interfaces into their SoCs," said Jurgen Beck, vice president and general manager at Keysight Technologies. "Our measurement tools and Synopsys' new D-PHY IP help support and develop the entire MIPI ecosystem, and we look forward to collaborating with Synopsys on future MIPI developments."
The new DesignWare MIPI D-PHY is available now in 16-nm FinFET processes, with availability in 28-nm processes scheduled for early 2015. VIP for MIPI D-PHY v1.2 is available now.
