Massive rise in usage of RISC V processor IP in VLSI chip designs lead to open era of computing and it is termed as monumental shift. RISC V has made incredible progress in this direction. The RISC V core market is estimated to grow at 115% CAGR from 2019 to 2025, where it is going to be present in 14% of all CPU cores by 2025. It is projected that from use of 2 billion RISC V cores in 2021, it will double to 4 billion RISC V cores in 2022 and again double to 8 billion RISC V cores in 2023. Zero-license and royailty-fee free RISC V is supported by rapidly growing chip design and embedded software ecosystem. IOT and embedded space is already an area, where RISC V finds a fertile space to grow with no notable weakpoints it has compared to ARM and other processor cores.
A full world of opportunity is open to growth-hungry electronics' entrepreneurs. A super-powerful combination of RISC V and Linux (the hardware and software) available to everyone.
Since RISC V is open-source IP, it can be used by top semicon maker such as Intel, or top fabless chip maker such as Qualcomm or a student hobbyist to your worst competitor. It is an expanding space, where no one owns and controls this processor IP. Though expanding, this space may also get quickly crowded.
In this article let's look at leading (top-25) chip makers who have developed RISC V based products and IPs:
Western Digital was the earliest leading semiconductor company adopting RISC V in its semiconductor chip design. The four RISC-V IP cores developed by Western Digital are, 64 bit, multicore SweRV Core EHX3 and 32 bit SweRV Core EH1, EH2 and EL2 RISC V cores. More on this available at https://www.westerndigital.com/solutions/risc-v
Renesas is another top ranked chipmaker who has made avaialable general-purpose microprocessors with RISC-V CPU Core. The Linux capable 64-bit IC family named RZ/Five (RISC-V) packs RISC-V CPU Core (AX45MP Single) 1.0 GHz, 16-bit DDR3L/DDR4 interface and supports interfaces such as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as entry-class social infrastructure gateway control and industrial gateway control. Renesas selected AndesCore' 32-bit RISC-V CPU cores to design its RISC V powered chips. Renesas has also used DR1000C RISC-V-based parallel co-processor in its RH850/U2B automotive SoC designed for electronic control unit. Renesas in partnership with RISC V specialist VLSI IP company SiFive developing RISC V based automotive MCUs for applications requiring massive processing such as ADAS, and Autonomous Driving.
Link to Renesas' RISC core powered products:
Microchip is offering a broad range of soft RISC IPs and other development eco support (called Mi-V RISC-V Ecosystem) for its programmable logic' customers. Microchip entered FPGA market after acquiring Microsemi, which had acquired a pure FPGA company called Actel. Family called PolarFire SoC FPGA pack deterministic RISC-V CPU cluster, providing five hardened RISC-V cores.
For more details visit: https://www.microsemi.com/product-directory/fpga-soc/5210-mi-v-embedded-ecosystem
Intel FPGA division has made available Nios V, a soft processor for Intel FPGAs ((earlier Altera) based on the open-source RISC-V Instruction Set Architecture. This processor is available in the Intel' latest Quartus Prime Pro Edition Software. Intel has big plan and it want to drive the RISC eco and become a foundry partner for fables RISC embracers.
Huawei to save itself from US restrictions on its Arm designs, Huawei chip making division called HiSilicon is using RISC-V architecture and released its first RISC-V board for Harmony OS developers. The main controller Hi3861 uses 32-bit RISC-V core operating at 160MHz. For more details visit: https://consumer.huawei.com/ph/community/details/Huawei-s-HiSilicon-Develops-First-RISC-V-Design-to-Overcome-Arm-Restrictions/topicId_129726/
There are dozens of other companies and organization who are developing RISC V IP based products. In the next article as continuation to this, we will share companies other than top chip makers opting and supporting RISC V.