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Date: 02-09-22

Open source chip design: The big picture of RISC-V ecosystem is emerging

With the availability of open source processor architecture  RISC-V  for the worldwide chip design community and the industry, we are seeing a continuous rise in the launch of new semiconductor chips powered by RISC-V processor cores all the way from simple commercial grade IoT MCU chips to functional safety automotive to aero-space grade high-rel processor chips.

In this article we try to provide you design software/tools companies offering product and support service to RISC-V based chip designs from small companies to biggest chip design experts such as Intel. The whole chip industry is embracing RISC-V. The growth of ecosystem around RISC-V is like a rising tide.

RISC-V development platforms:

Alibaba owned  China focused semiconductor  chip design business called T-HEAD  launched chip development platform to develop open source RISC V based SoC chips. T-HEAD while offering its own  AI SOC chip for edge computing, it also develops and owns set of processor IPs. It has adopted open source RISC-V based processor architecture extensively. T-HEAD is a very China based company having offices only China and looks like it intend to support mainly China based chip developers on RISC V based SOC chip development by offering a development platform called Wujian 600.

However it has hardly given any particulars on its website in English language on any further details of its offerings. We unable to figure out what are the IPs it is offering, and any EDA software, test and verification support. However there is a Chinese language information on this development platform, which we unable to make out the exact details of its offering.   

Wujian 600 is for developing edge SOCs  for applications such as  home robots, medical imaging and video conferencing. The release also says the development platform includes optimised software stack to support quick development of IC products. The benefits of the platform includes bringing down the development cost and reducing the design cycle of chips. The platform  is resourceful enough to run Firefox browser, and LibreOffice on a open source Linux-based operating system called OpenAnolis.

T-Head is already known for its  successful launch of  Wujian 100 open platform to develop microcontroller chips  based on RISC-V.  There are lot of Chinese companies and developers who have leveraged  this  platform  to develop RISC V based MCUs.

Here is the link to know more on T-HEAD's platform:
https://occ.t-head.cn/?spm=a2ouz.12986968.0.0.42dc1384MLE4vi

If this is about Alibaba's  T-HEAD.  World's number one semiconductor technology leader Intel gets into  open source chip design activity in a big way by launching  development platform called Pathfinder. Intel getting into this kind of activity is new and significant. The way Intel is branching out to new paths of semiconductor technologies tells lot more wonderful times for silicon technology.  The Pathfinder is a unified integrated development environment  or  call it a ecosystem involving  VLSI IP providers,  EDA software  and tool-chain companies,  operating systems,  and any technology providers supporting  integrated circuit chip development.

Pathfinder is available in two editions,  one for  students and hobbyists with lesser commercial features  and the other for the commercial developer featuring lot more silicon IP,  and wider technology/support.  For commerical purposes, Intel supports companies in the production of chips through its Intel FPGA for low volumes, Intel eASIC for medium volume and Intel Foundry Services for large volume.

 The below image/ table  gives you  the difference between starter and Professional edition.
 

Unlike Alibaba's T-HEAD, Intel clearly provides step by step getting started details as shown in the image above.

 

Partners involved in this pathfinder  project  and  their role/ product  involved:

EDA tool provider Cadence is leading provider of  vision DSP,  whose IP  is part of professional edition of  Pathfinder.

Check Point Software Technologies collaborating with Intel  where it's  security product called quantum IOT protect is made available  on Intel's Pathfinder  platform.

Miri Ofir, R&D Director at Check Point Software commented: “Cyberattacks are increasing in number and sophistication all the time. It has never been more important for IoT device developers to prioritise cybersecurity, not just to win a competitive edge or comply with emerging regulations but to give their end customers enterprise grade security and peace of mind.”

Andes Technology: Andes is a premier  member of  RISC-V International. This company's  popular 64-bit superscalar multicore AX45MP processor IP and 64-bit vector processor core NX27V with up to 512-bit vector length, both pre-integrated with AXI-based AE350 platform, have been made available in the Intel Stratix 10 GX FPGA Development Kit, which is part of the  FPGA boards  offered by  professional edition of  Pathfinder.

The other partners of pathfinder includes: Amazon AWS, Chips Alliance, Codasip, Codeplay Software, Crypto Quantique, Fraunhofer IMS, IOTech Systems, MIPS, Imperas, OpenHW Group, RISC-V International, Siemens EDA, SiFive, SOC.One, STMicro, Terasic, amd Zephyr Project.

Link to Intel Pathfinder: https://pathfinder.intel.com

Design Verification Support:

To support important step of design verification needs of open source VLSI design community and also commercial development of RISC V based SoC chips,  Imperas Software has made available first open-source SystemVerilog RISC-V processor functional coverage library for RISC-V cores. Initial release for RV32IMC, RV64 instructions covers both commercial as well as academic.  Company soon to comeout for other architectures of RISC-V.

Imperas is headed by Simon Davidmaan, the CEO of this company who has played critical role in the development of SystemVerilog.

“The open standard ISA of RISC-V provides great flexibility for innovation in the design of modern processor implementations,” said Simon Davidmann, CEO at Imperas Software Ltd. “With all the configurability offered by the standard extensions and implementation options, plus users-defined custom features, the total scope of the RISC-V verification effort cannot be understated. Through our experience working with some of the most sophisticated customer designs we recognize the usefulness of ready-to-use SystemVerilog Verification IP that allows developers a solid foundation on which to build a successful DV plan.”

“Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture,” said Allen Baum of Esperanto Technologies, Inc., and Chair of the RISC-V International Architecture Test SIG. “The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.”

The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, latest test suites and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is now available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.

Earlier in the month of July this year Imperas has also provided to this design community, the  latest updates for  RISC-V Verification Interface (RVVI) for RISC-V processor verification with virtual peripherals to support asynchronous events and system level interrupts.

Here are the interesting comments from industry experts in this field:

“An open verification standard such as RVVI provides the essential framework and guidelines to configure the test environment for RISC-V and allows the flexibility necessary to address all aspects of a modern processor yet maintain a common base that allows verification IP reuse across projects,” said Melaine Facon, Director of Codasip’s French Design Centre, (https://www.codasip.com). “With the latest additions to Imperas’ tools processor DV teams can pre-test system level integrations and cover the next level of complex asynchronous events with virtual components integrated into the test bench. These guidelines both support entry level verification and also enable experts to build compressive test environments for the most complex RISC-V designs.”

“New design innovations with RISC-V offer great potential in automotive applications, but achieving the extensive quality standards are critical for success,” said Hideki Sugimoto, CTO of NSITEXE, Inc., a group company of DENSO Corporation. “The verification requirements to achieve the ASIL D safety requirement level of ISO 26262 with a processor-based design are extensive, however verification IP reuse through standards such as RVVI help improve efficiency and achieve time to market schedules with all the design innovations that RISC-V enables.”

“One aspect that all RISC-V processor designers agreed on, both commercial vendors and open-source developers, is that quality is the key to successful IP core adoption,” said Rick O’Connor, President & CEO OpenHW Group. “The OpenHW Group have supported the adoption of RVVI from its inception through the member contributors in the OpenHW Verification Task Group, and now welcome the new features and growing adoption by the commercial community.”

“As a developer of leading high-performance RISC-V application processors, verification standards are an important companion to the RISC-V specifications,” said Itai Yarom, VP of Sales and Marketing at MIPS. “Verification standards such as RVVI provide a solid foundation that supports all RISC-V adopters, from basic embedded cores through to complex application processors with multi-cluster, multi-core, multi-threading and out-of-order pipelines.”

“As the leading provider of commercial RISC-V Instruction Stream Generators, it is essential for verification standards for test benches and verification IP reuse to evolve,” said Shubhodeep Roy Choudhury, Managing Director & Co-founder, Valtrix. “Adopting RVVI virtual peripherals provides additional flexibility and efficiency for our flagship verification product STING to target asynchronous event verification, which is essential for quality RISC-V processor functional design verification.”

“All the significant progress in processor innovation can be traced back to two fundamental building blocks: Abstractions and Standards,” said Simon Davidmann, CEO at Imperas Software Ltd.  “Simulation of the latest designs with billions of transistors is achieved through abstraction, similarly the success of IP reuse has been enabled by standards. Now the emerging RISC-V verification ecosystem can build on the open standard RVVI flexible framework as a basis for verification IP and quality testing methods.”

To tell you one more important latest development to help chip designers in design reuse of verification IP and also to improve efficiency of verification, Imperas partnered with Breker to develop interfaces and standards to unify the functional verification design flows.

“RISC-V represents an inflection point for semiconductor verification as the design freedom provided by the open ISA means an assumption of the responsibility of the processor and system verification task,” said David Kelf, CEO at Breker Verification Systems. “In partnering with Imperas, the leaders in RISC-V processor verification, we can offer a combination of technologies and interface standards for IP and SoC testing that ensures commercial grade verification for these flexible devices right through to the end platform.”

“RISC-V marks the end of the one-size-fits-all approach to processor IP, now all SoC developers can explore new innovations with processor IP configured for the target application,” said Simon Davidmann, CEO at Imperas Software Ltd. “Many of our customers are exploring the design side possibilities of new processor architectures and their implications for SoCs and systems in parallel, extending the verification scope from IP cores to system level integration. With Breker’s proven system verification experience, we are streamlining the critical verification tasks to enable the full potential of RISC-V based devices with commercial-grade verified quality.”

Imperas said in one of its earlier release that its ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on 2nd generation designs. Some of the customers named by Imperas includes: Codasip, Swatch owned EM Microelectronics, Denso owned NSITEXE, Nvidia Networking (Mellanox), OpenHW Group, MIPS Technology, Seagate Technology, Silicon Labs, and Valtrix Systems.

 Functional Safety design using RISC-V:

RISC-V is becoming a choice for automotive grade chip development for its inherent advantages. Automotive domain requires chips fulfilling functional safety requirements compliant with IS26262. One notable semiconductor VLSI design  company working in this domain is Japan-based NSI-TEXE, subsidiary of Denso. NSI-TEXE is developing RISC-V based processor semiconductor IP and related software for functional safety applications.  It has developed RISC-V based parallel data flow processor IP  DR1000C for offloading some heavy computing loads from microcontrollers.  DR1000C is a MIMD  based embedded vector processor certified for  ISO 26262 ASIL D. This IP consists of RISC-V 32bit  based scalar processing unit, RISC-V vector extension -based vector processing unit and a control core unit. The safety related features such as  error correction code (ECC) for memories, dual-core lockstep architecture, bus protocol violations detection, and an error management are integrated into  this IP to meet tough  ASIL D safety requirements. This technology is licensed to leading automotive chip maker Renesas for use in its automotive grade RH850/U2B microcontrollers (MCUs).

To learn more on this and some more RISC-V based processor IP cores this company is offering, visit the company website https://www.nsitexe.com/en/

Leading semiconductor VLSI chip design EDA software companies, mainly  by the trio gang, Synopsys, Cadence and Siemens all are supporting development of RISC V based processor chips.
Synopsys had arranged a webinar on 31st of August 2022 conducted with the participation of  NSI TEXE. The topic of the webinar was “Accelerating Software Development for ASIL D Processor IP Using Synopsys Virtual Prototyping Solutions.”  The speakers at the event were: Dr. Tim Kogel, Principal Engineer Synopsys and  Dr. Masayuki Ito, Director of Business Promotion, NSITEXE, Inc.

The URL to know more about this event is: https://www.nsitexe.com/en/news/archives/20220823_1/    

Other Design Tools, OS for RISC V

Ashling and Embecosm are into the fifth year of their partnership in developing RISC V based tools including Compilers, IDEs, Debuggers, SDKs and Debug and Trace probes. Both the companies have membership  in OpenHW Group, to collaborate on the development of a RISC-V based Development Kit and SDK. To read more on this visit: www.eeherald.com/section/news/p20220704nw22.html

Siemens Digital Industries Software which had acquired world's 3rd biggest EDA software vendor Mentor Graphics has made available its Nucleus ReadyStart solution for embedded development  based on RISC-V  processor architecture.
 
Nucleus ReadyStart  is a ready to use software  package  holding software, IP, tools and services in a single  solution  designed for   high reliability applications such as aerospace, automotive, industrial, medical, and  also for general embedded  applications.
 
“Nucleus ReadyStart for RISC-V addresses the requirements needed for today’s advanced and secure edge-to-cloud devices with proven technology,” said Scot Morrison, vice president and general manager, Embedded Platform Solutions at Siemens Digital Industries Software. “Providing a robust and integrated solution for RISC-V devices is critical for embedded developers today, especially with the competitive pressures to deliver innovative devices with shortened time-to-market and cost constraints. Nucleus ReadyStart for RISC-V includes SMP, POSIX, Debug Agent, and security protocols from wolfSSL/OpenSSL. Users can also connect their device to the cloud with the Nucleus IoT Framework Add-on which supports several cloud services and providers such as Amazon Web Services (AWS), Microsoft Azure and MindSphere, the industrial IoT as a service solution from Siemens. These new capabilities enable RISC-V-based embedded developers to customize rich features to meet the needs of today’s advanced device manufacturers.”

Bluespec is a long time supporter of RISC-V where it had launched Bluespec RISC-V Factory to provide RISC-V developers a new set of resource to design with RISC-V open source cores far more safely and efficiently.

Bluespec has open sourceed its BSV development tools since Feb 2020 which is very useful for RISC-V developers. It's CEO Charlie Hauck has commented  “Open source collaborative development is the only way to deliver the HDL advances necessary for leading-edge applications requiring security, AI, and high assurance. Formal verification, one of the most critically needed advances, requires access to HDL tool source code to provide a complete chain of proof.”

Neel Gala, project member of  RISC-V based India's Shakti processor project  has said  “Bluespec System Verilog gives you a high-level abstraction, like going from assembly [level programming] to C. You don’t do the dirty work, the compiler does all the work for you. You work at a much higher level, your throughput increases. Simulation and turnaround time decreases, and your product release time has a shorter cycle.”

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