Semicon equipment spending down by 16% in 2012, says Gartner
Date: 22/04/2013
Gartner finds worldwide semiconductor capital equipment spending totaled $37.8 billion in 2012, a 16.1 percent decline from 2011. Gartner says Wafer-level manufacturing under performed the market in 2012, pulled down by weakness in lithography and deposition. Among the major sectors, those more strongly driven by logic manufacturing, 28/20-nanometer (nm) processing and yield ramps-ups did better.
"Continued oversupply in DRAM and the shift to NAND into oversupply led to a reduced need for capacity," said Klaus-Dieter Rinnen, managing vice president at Gartner. "Memory manufacturing-related purchases declined significantly. Logic-related spending provided only a weak counterforce, impacted by slowing overall semiconductor device demand in the second half of 2012 and bulging inventories. Consequently, manufacturing equipment sales realized a declining quarterly pattern, starting in the second quarter through the end of the year."
Applied Materials reclaimed the No. 1 spot based on its relative strength in deposition and process control (see table below). Weakness in lithography and limited sales in extreme ultraviolet (EUV) caused ASML's decline. Similar to Applied, Tokyo Electron Ltd. (TEL) benefited from its relative strength in the nonlithography sectors it serves. Lam Research moved into the No. 4 position with its merger with Novellus Systems.
Source: Gartner (April 2013)
"Notable is the further rise of the sales share of the top 10 vendors, now approaching 70 percent, compared with 61 percent in 2008," said Mr. Rinnen. "The advance of these large players symbolizes losses of smaller players in the competitive race and an increasing market dependence on a few vendors in the equipment market."
Other research points shared by Gartner on Semicon equipment market:
The back-end segment, and especially the wafer-level packaging (WLP)-related segments, outperformed the market. These segments were either tied to the relative strength of logic investments, such as advanced RF or system-on-chip (SoC) test equipment, or to the increasing popularity of bump, flip-chip and other WLP processes, such as stud bump bonding and wafer bonders for through-silicon vias (TSVs).
The process control segments outperformed the total wafer fab equipment market as companies ramped up production at the 32/28 nm node and needed increased inspection and defect review tools to monitor increasingly complex processes. Within the process control segments, e-beam patterned wafer inspection saw the best performance, up 36 percent in 2012.
