ARM simplified design of SOC chips for low-power applications using UMC's 55 nm semiconductor chip manufacturing process. ARM has partnered with UMC in offering ARM Artisan physical IP solution on 55nm. UMC 55 nm ultra-low-power process is gaining some level of popularity for development of embedded systems and Internet of Things (IoT) applications. 55 nm, being a well established and less expensive node, serves many of the popular applications in IOT.
UMC 55 nm ultra-low-power process supports features such as thick gate oxide, multi-channel library options so that power consumption can be minimised in SOCs for IoT applications.
"A complete physical IP foundation platform at UMC's 55ULP process technology is vital in enabling low-power and cost-sensitive designs for emerging IoT applications," said Will Abbey, general manager, physical design group, ARM. "By delivering libraries optimized with features targeting power-efficiency, ARM and UMC are providing SoC designers with a comprehensive set of new tools."
"IoT silicon designers are being asked to deliver more highly integrated solutions within more power constrained environments, and more quickly," said Shih-Chin Lin, senior director of IP development and design support division at UMC. "UMC possesses the foundry industry's most robust IoT-specific 55nm technology platform, supported by highly comprehensive IP resources to address the "always on" ultra-low power requirements of IoT products. The addition of Artisan Physical IP to our 55ULP platform immediately increases the breadth of tools we can offer to reduce complexities and time to market."
The Support available in Artisan libraries as per ARM:
"The 0.9v ultra-low voltage domain, thereby saving up to 44 percent dynamic power and 25 percent leakage power when compared to 1.2v domain operation
Multi-channel libraries with multiple Vts to offer SoC designers leakage and performance options. Long channel libraries can be used to further reduce leakage by up to 80 percent. The Power Management Kit (PMK) enables both active and leakage power mitigation.
Innovative thick gate oxide library will offer dramatically reduced leakage (350x lower than regular standard cells) for always ON cells. The ability of this library to interface with higher voltages (including battery voltages used in IoT devices) can also offer the advantage of negating the need for a voltage regulator."
The high-density memory compilers offer multiple integrated power modes to save state while minimizing standby leakage. Utilizing these modes will allow SoC designers to realize up to 95 percent lower leakage when compared to regular standby says ARM.
The UMC-based physical IP for 55ULP is available immediately via ARM's DesignStart portal.