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Date: 06-03-15

New AXI4 verification IP from eInfochips for FPGA and SoC designs

India based VLSI design services company eInfochips has announced the availability of the AXI4 Verification IP (VIP) to improve reliability of FPGA and SoC designs based on the popular ARM AMBA 4 architecture. The solution already supports AXI4 and AXI4-Lite, and will have AXI4-Stream variant available in Q1 FY16. eInfochips AXI4 VIP is a plug-and-play solution developed in SystemVerilog, and is available for OVM, VMM and UVM verification methodologies. The eInfochips AXI4 VIP can be introduced to an existing verification environment as a retrofit.

Parag Mehta, the Chief Marketing and Business Development Officer at eInfochips said, “Reliability is non-negotiable in the semiconductor industry, and so is time-to-market. We are key enablers for both these parameters for leading global corporations. Our VIPs, combined with our verification, implementation and DFT services have enabled more than 150 tape-outs already.”

The eInfochips AXI4 VIP supports functional coverage for checkers to ensure the IP/RTL behaviour is continuously monitored. For faster debug cycles, eInfochips AXI4 VIP has features such as TRANSACTION TRACKER and BANDWIDTH MONITOR.

The complete feature set and specifications data sheet can be found: https://www.einfochips.com/images/solutions/Datasheet-AXI_4.0.pdf

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