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Date: 29-11-14

Low jitter clock synthesizer for serial data communications

Integrated Device Technology introduced 10-output clock synthesizer for serial data communications systems. 8T49NS010 synthesizer with an integrated fanout buffer/divider generate low jitter clocks for 40GE and 100GE telecommunications and networking systems.

The 10-output synthesizer provides a high-frequency clock with 86 fs RMS phase jitter over the standard 12 kHz to 20 MHz integration range. The 8T49NS010 features an integrated fanout buffer, removing the issues of additive phase jitter and noise coupling from oscillator to fanout buffer. The chip supports programmable configurations and output levels to satisfy the requirements of a variety of applications.

“The 8T49NS010 synthesizer delivers ultra-low jitter required for high-speed communications,” said Louise Gaulin, vice president and general manager of IDT’s Network Communications Division. “The device provides engineers with a simple, yet ultra-high-performance solution.”

The 8T49NS010 is configurable through an I2C serial interface and operates over an industrial temperature range. In addition to output power-down, it supports two logic levels for its differential outputs; the first provides an LVPECL output level with 750mV typical swing, while the second provides a similar swing and output level with no external DC termination. The device uses an external fundamental mode crystal to save cost.

Detailed specs include:
Typical phase noise jitter of only 86fs from 12kHz to 20MHz
An LVPECL output level with 750mV typical swing requiring no DC termination
Noise floor of -161 dBc/Hz

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