FPGA based new ref design for IEEE 802.3 MDIO interface controllers

Lattice Semiconductor Corporation published MachXO3 FPGA based new reference design for IEEE 802.3 Management Data Input/Output (MDIO) interface controllers for engineers quickly implement optical Ethernet designs up to 100Gb/s. Designers can use the reference design to implement a simple Wishbone user logic interface that enables the user to access the PHY registers. It supports MDIO IEEE 802.3 Clause 45/22 master/slave controllers and features pre-amble pattern selection through the input port.