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Date: 16-01-14

VLSI Design: HEVC decoder silicon IP from oViCs consumes 840K gates

High Efficiency Video Coding (HEVC) is becoming an important video encoding decoding standard for compressing more data as well as for producing high resolution video content such as Ultra high definition (4K UHD). HEVC compresses the video data 2X better than the MPEG-4, so for the same amount of video compressed data, you can get double the resolution of MPEG-4. An U.S. based start-up named oViCs is offering silicon IP exclusively for HEVC coding and also for H.265/MPEG-H. oViCs claims its solutions offer low latency and on the silicon they occupy less gate count, works at low clock speed and lesser power consumption.

oViCs says "The implementation complexity of HEVC is about five times higher than H.264, and a brute force approach cannot provide the low power and low latency required by the mobile services."

It looks like for the high-definition video related product design companies, it is becoming must to support HEVC encoding and decoding.
Here are some key information for VLSI design engineers who wish to use the silicon IP in their SOC chip design:
Logic gate count:700 Kgates (840 Kgates for 10-bit)
Memory: 108/128 KB SRAM for 8/10-bit 1080p480
151/179 KB SRAM for 8/10-bit 4K120
Area: 0.5 mm2 fully routed, w. scan & BIST (20nm)

VLSI design engineers can learn more on oViCs's HEVC product called ViC-1 HEVC 4Kp120 Decoder at http://ovics.com/products/

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