Date: 7th Jun 2011
PDK for 0.18µm HV CMOS technology
for austriamicrosystems' foundry
austriamicrosystems business unit Full Service Foundry
has announced the availability of two new analog/mixed signal
high performance process design kits ("HIT-Kit")
for its 0.18µm High-Voltage CMOS technology H18. Jointly
developed with IBM, the 0.18µm High-Voltage CMOS process
is the 6th generation of continuously improved High-Voltage
CMOS technologies developed at austriamicrosystems.
austriamicrosystems says based on Cadence Virtuoso custom
design platform (both, IC 5.1.41 and 6.1.4 releases), the
new HIT-Kits significantly improve the time-to-market for
highly competitive products in the analog intensive mixed
signal, smart sensor and System-on-Chip arena.
Both new HIT-Kits, version 3.78 (qualified for IC 5.1.41)
as well as version 4.01 (qualified for IC 6.1.4) support
the 0.18µm specialty process technology H18 (High-Voltage
CMOS) which is based on IBM's industry proven foundry process
technology CMOS7RF.The kits come complete with silicon-qualified
digital, analog and RF library elements, complete sets of
low voltage devices (1.8V and 5.0V) and high-voltage devices
with various gate oxide thicknesses (20V and 50V devices).
Fully characterized simulation models, extraction and verification
run sets for both, Calibre and Assura and automatic layout
device generators (pcells) are included. Routines such as
Safe Operating Area verification tool (SOAC) and Life-Time
simulation tool are included in the kit.
"The H18 process is already the 6th generation of
High-Voltage CMOS processes developed at austriamicrosystems
and it is now ready for design and volume production. Both
new HIT-Kits are a result of austriamicrosystems' continuous
efforts to deliver best-in-class design environment and
analog foundry services to our customers" states Thomas
Riener, Senior Vice President and General Manager of austriamicrosystems'
Full Service Foundry business unit. "Offering two new
HIT-Kits supporting different Cadence versions provide full
flexibility to our customers and enable them to easily start
design activities with our 0.18µm High-Voltage CMOS
specialty process in a broad range of smart green applications
such as power management and LED driver applications."
The digital standard cell libraries included in this H18
HIT-Kit have a gate density of 118kGates/mm² and are
available both in standard and low leakage versions. All
I/O structures within the design kit are silicon-validated
and meet the military ESD and JEDEC latch-up standards with
I/O pads designed to surpass 4kV HBM and 250mA latch-up
immunity.
To know more visit http://asic.austriamicrosystems.com/hitkit401.
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