Magma's upgraded version of Talus Design uses a single binary file database called Volcano to store complex VLSI chip design input files. This binary file database Volcano captures all the design data for the physical synthesis part of the chip design i.e. RTL-to-GDSII design flow. It's like funneling the design input files at backend, a reverse shape of bursting real volcano.
Upgraded version of Talus Design features enhanced timing optimization engine, improved memory efficiency. Magma says, VLSI designers can fully optimize and accurately predict final chip performance early in the design cycle and minimize design iterations.
Media processor developer, Sigma Designs is the early adopter of this tool for developing its recent chip tape-outs.
Talus Design is said to synthesize multimillion-instance RTL designs without hierarchical partitioning or guard-band-related timing constraints.
Any small changes done at RTL stage is propagated up to final stage of design flow automatically without adopting manual process of recompiling the entire design. The languages supported include VHDL, Verilog and System Verilog.
The timing mismatches are avoided between synthesis and physical design by using a unified data model and single static timing analyzer throughout the Talus RTL-to-GDSII flow.
For details visit www.magma-da.com