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  Date: 12/06/2016

Cadence and Synopsys supports SMIC' 28 nm low-power process

Cadence' physical implementation tool Innovus, Timing Signoff tool Tempus, cell-level power signoff tool Voltus IC Power Integrity, Voltus-Fi Custom Power Integrity Solution, Conformal Low Power Verification, Quantus QRC Extraction Solution, Cadence Physical Verification System (PVS), Cadence CMP Predictor, Litho Physical Analyzer (LPA) now supports SMIC 28nm reference flow.

Another EDA vendor Synopsys joined hands with SMIC and announced the immediate availability of 28-nanometer (nm) RTL-to-GDSII reference design flow. The flow is based on Synopsys' Galaxy Design Platform using IC Compiler II place and route solution, Design Compiler Graphical synthesis, StarRC extraction solution, PrimeTime signoff solution and IC Validator physical verification solution.

Synopsys' IC Compiler II powered reference flow supports low-power techniques such as power-aware clock tree synthesis, power gating and physical optimization, enabled by industry standard IEEE-1801 UPF (Unified Power Format) power intent.

The Lynx technology plug-in for the SMIC 28-nm HKMG process helps in improving automation and visualization capabilities.

 
          
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