VLSI chip design IP core news this week
ARM Made available of its Artisan physical IP including POP IP for mainstream mobile SoCs based on the new ARM Cortex-A73 processor on the TSMC 16FFC (FinFET Compact) process.
Arasan announced availability of its MIPI DPHY IP Core Ver 1.2 supporting data speeds of up to 2.5 Gbps per lane, on the TSMC 28nm HPC fab Process also soon be ported to TSMCís latest HPC Plus Process. This latest DPHY IP uses Patent Pending DPHY architecture that optimizes the DPHY design for ultra low power and area.
Digital Blocks has announced its DB9000 TFT LCD Controller IP Core supports LCD panel resolutions from 240x240 up to 8192x8192, with 1,2,4,8,10,16,18,24,30 and 32-bit bits-per-pixel, both RGB and YCrCb color spaces, 1, 2, 4, & 8 port LVDS interfaces, as well as MIPI DSI, DVI, HDMI, V-by-One, and DisplayPort interfaces.
The DB9000 IP Core supports SoC fabrics interfacing to SDRAM frame buffer memory with 32-, 64-, 128-, or 256-bit data widths, supporting AXI4, AXI3, AHB, AHB-Lite, OCP, and Avalon protocols. With respect to the AXI protocol, the DB9000 supports multiple outstanding memory requests, supporting the most demanding, highest resolutions panels.
Cast has sold a GZIP data decompression IP core to a Tier 1 vendor producing wireless mobile communications chipsets, where this IP is used to process compressed firmware stored in Flash memory on LTE chips primarily targeting the IoT market. Cast helps its customers to implement this IP within 40 K gates and developing a DMA capable interface wrapper custom-tailored for efficient bandwidth utilization in the customerís specific SoC architecture and bus fabric.