VLSI design companies press the throttle lever of cache coherent interconnect tech
These days from supercomputers to smart phones, computing accelerators such as graphic accelerators are helping to improve the computing speed. There is significant amount of digital data such as high-definition video, big data, search engine, 5G data, where DSP or FPGA can analyse and process faster than the traditional CPU. All this suggests future SOC's along with multiple number of CPU cores will have graphic accelerators and FPGA-based media processing accelerators. Even the personal computers are seeing the benefit from such accelerators in particularly PC gaming applications. FPGA inside a PC can enhance the gaming performance lot better by making it faster and also at less power consumption. This trend of heterogeneous computing driving VLSI companies to join hands to come up with an open acceleration framework.
AMD, ARM, Huawei, IBM, Mellanox, Qualcomm, and Xilinx collaborate on new Cache Coherent Interconnect for Accelerators (CCIX) that will allow multiple processor architectures and accelerators to seamlessly share data. The companies are collaborating on the specification for the new Cache Coherent Interconnect for Accelerators (CCIX). This results into a interconnect specifications to connect processors with different instruction set architecture and coherently share data with accelerators in a heterogeneous computing atmosphere. FPGA maker Xilinx has already announced the its 16 nm finFET FPGAs will have multi-terabit memory bandwidth supporting cache coherent interconnect for acceleration technology. For more information on CCIX visit http://www.ccixconsortium.com/.