Electronics Engineering Herald                 
Home | News | New Products | India Specific | Design Guide | Sourcing database | Student Section | About us | Contact us | What's New

News

  Date: 26/06/2014

15th EDA event from Synopsys was houseful

Synopsys just finished hosting its 15th Synopsys Users Group (SNUG) conference in India to help engineers better address the productivity challenges they face when designing today’s chips and electronic systems. The conference, which has grown into the industry’s largest gathering of semiconductor professionals in India, highlights advancements in semiconductor design and verification that can be used to design even the most complex systems-on-chips (SoCs). More than 2900 leading SoC and system designers who are Synopsys tool and technology users attended the two-day conference June 25th and 26th at the Leela Palace in Bangalore, making it the largest SNUG India event to date. Launched in 2000, SNUG India is part of a global program that began in 1991 and includes 14 user conferences with nearly 10,000 participants around the world.

SNUG India 2014 featured 39 user papers that discuss a range of topics, including early exploration, low power implementation and verification, test, mixed-signal verification, emulation and FPGA prototyping. Many of the papers presented address key challenges such as improving design productivity, achieving better quality of results (QoR) and designing for advanced technology nodes. In addition to the user papers, Synopsys offered 19 tutorials to showcase advances in tools and IP to help meet future design and technology challenges. A conference highlight was a peek into new game-changing design solutions from Synopsys, including the IC Compiler II system and the Verification Compiler platform.
In his opening-day keynote address, Dr. Aart de Geus, chairman and co-CEO, Synopsys, Inc. discussed how the challenge for designers to keep pace with today’s rate of change has never been greater.

AART

Above Pic: Aart De Geus addressing at SNUG India

“The rising complexity in semiconductor techonomics—the intersection of technology and economic realities—is driving a massive momentum towards ‘smart everything,’” said Dr. de Geus. “With rapid innovation in both traditional and emerging application domains, the semiconductor design community is at the heart of some of the most exciting and important changes in human history. Yet in the midst of this whirlwind of change, the foundational challenge for all successful ecosystem players remains the same: they must make sure that the technology differentiation they offer actually creates economic value for those downstream.”
In his presentation, Dr. de Geus gave an overview of many years of investment and innovation by Synopsys to enable designers to address this massive rate of change. Results of these investments have been significant new productivity advancements in Synopsys’ design and verification platforms.
Dr. Pradip Dutta, corporate vice president and managing director, Synopsys India, said, “SNUG India offers a valuable opportunity for the chip design community to connect with each other and to interact with Synopsys executives and technologists. It also provides a forum for attendees to benefit from peer-reviewed technical papers and insightful keynotes from industry leaders.”
Raman Santhanakrishnan, managing director, LSI India shares his experience as a valued customer of Synopsys: “An event like SNUG benefits the user community. To me, SNUG is a great collaborative platform. It is a platform wherein some of the industry’s best experts converge and share their best practices and provoke some of the best ideas.”
A conference of this nature would not be successful without industry participation. SNUG India Platinum Sponsors include ARM, GLOBALFOUNDRIES, Imagination Technologies, Samsung and TSMC.

News Source: Synopsys
Author: Srinivasa Reddy N
Header ad

 
          
ADVT
Home | News | New Products | India Specific | Design Guide | Sourcing database | Student Section | About us | Contact us | What's New
©2012 Electronics Engineering Herald