Accellera enhances mixed-signal modeling and verification in Verilog-AMS std
Accellera Systems Initiative has developed new verification and design modeling extensions for its Verilog-AMS standard. The revised language reference manual is available for download from www.accellera.org.
The revised standard, Verilog-AMS 2.4, includes extensions to benefit verification, behavioral modeling and compact modeling. There are also several clarifications and over 20 errata fixes that improve the overall quality of the standard.
The Verilog-AMS WG is currently exploring options to align Verilog-AMS with SystemVerilog in the form of a dot standard to IEEE 1800.
To know more visit www.accellera.org