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  Date: 19/01/2014

Top VLSI design white papers at Aldec

EDA design software vendor Aldec has done a appreciable job in providing learning material and online training courses on latest technologies to VLSI design engineers. The announcement news titled "VLSI design: Free online UVM training from Aldec" we published in EE Herald is one of the most read articles in year 2013. Aldec has listed the below white papers which have received highest downloads in 2013 which are available on Aldec's website.

1. Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms

The most commonly used approach to analyzing objects in an HDL design, is based on the well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient

2. DO-254: Increasing Verification Coverage by Test

Verification coverage by test is essential to satisfying the objectives of DO-254. However, verification of requirements by test during final board testing is challenging and time-consuming. This white paper explains the reasons behind these challenges, and provides recommendations how to overcome them. The recommendations

3. Randomization and Functional Coverage in VHDL

Modern digital designs reach the scale of complete systems and require support of Constrained Random Test and Functional Coverage in verification. Although VHDL does not have built-in, direct support for those methodologies, there are neat solutions that allow their quick implementation in your testbench.

4. Corporate Standardization of FPGA Design Flow

Growing customer requirements and technological abilities increase the design complexity of hardware and software. Time to market is shortening as well as the lifetime of new designs. In order to meet all those requirements a new approach to the design process is required.

5. Making Floating-Point Arithmetic Work in Your RTL Design

Description: Floating-point arithmetic becomes a widely used format in digital system design. For example, DSP applications often demand high precision while operating with large dynamic ranges. The IEEE 754-2008 floating-point arithmetic standard fulfills this criterion but it might be extremely hard to comprehend and use.

You can find all these at http://www.aldec.com/support

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