SOC security design; fast emerging new area in VLSI design
SOC security design is fast emerging as another area of VLSI design, where expertise is evolving to protect the sensitive data in the physical part of the chip from hackers. Hackers may access the internal parts or the circuitry of the chip to make it malfunction or to access the identity and other such security sensitive data. If the security aspects of SoC design is not taken care, it will be difficult to prevent hacking on the physical hardware which includes both chip and board, the only solution in the case of hardware security breach, is to replace the physical device, which is expensive.
SOC designers adopting various techniques in processing and storing the sensitive data inside the chip. The attacks on SOC is classified as active and passive. People use sophisticated attacks such as advanced optics and shape recognition programs. The physical layer of communication function inside a chip is more prone to attacks. The Security is also broken by doing power analysis of signals, the power consumption pattern is studied to know the transmitted code in interconnects and buses.
To make SOC design more secure, various techniques have evolved and has become an interesting research area. Below we list some of the well-known techniques adopted in VLSI chip design:
1. The most basic thing to secure chip is to shield the device to maximum level from electromagnetic interference ( both emission and reception). No electronic signal should come out of the chip with open data.
2. No sensitive data should be stored in the register or cache after the completion of processing such data. So protection of registers and other storage memory areas is important.
3. There are various methods available to deceive the hacker from getting the data through simple power analysis or differential power analysis techniques. Sending dummy data along with the real data is one technique.
4. There is also a separate security verification tool available from Jasper called Security Path Verification App, which helps in detecting security vulnerabilities in SOC design.
Security Path Verification App verifies secure data communications and storage locations are protected from illegal access and unauthorized modifications.
Security Path Verification App enables the capture and verification of requirements that are not expressible in standard SystemVerilog Assertions (SVA), as per Jasper. It basically simulates tampering to verify the design is protected against attacks by using path sensitization technology.
Security Path Verification App allows users to specify the legal security access paths and enables users to identify potential security vulnerabilities in a SoC design by specifying functional paths between non-secure and secure areas. Jasper says this tool is already in demand and is used by leading chip companies.
To give you further information on learning methods to design security enabled SOC chip, you can find the pdf file at: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.106.5114&rep=rep1&type=pdf
Jasper has written a white paper on this subject. White Paper can be downloaded at
There is also an event named Cryptographic Hardware and Embedded Systems , which covers security related research in hardware design.
The company called Elliptic Technologies offering SoC security design services. It has published White papers on subjects such as Crypto processor, "Secret Key and Identity Management for System-on-Chip Architects", "Symmetric Cryptographic Offload Options for SoC Designers". These white papers can be accessed at http://www.elliptictech.com/en/knowledge-center/whitepapers