Altera demos interlaken connectivity between Cavium processors and Stratix FPGA
Altera has successfully tested the interoperability of Interlaken IP core on its Stratix V FPGAs with Cavium’s OCTEON multicore processors. Interlaken IP is used to connect chip to chip at high data-speed rates.
“Altera’s flexible Interlaken IP enabled us to quickly show interoperability between our products,” said John Bromhead, director, Solutions and Services at Cavium. “This solution gives our customers the added assurance that when they develop with Altera FPGAs and Cavium’s OCTEON processors, the devices will work seamlessly together. The ease of interoperability also helps customers meet tight time-to-market windows.”
The features of Interlaken IP core include:
Data rate and lane support up to 12.5G and x24 lanes
Standard and customized Interlaken IP cores offered
Fully integrated IP deliverable, includes MAC, PCS, and PMA layers
Interlaken Protocol Definition v1.2 compliant
“The flexibility of our Interlaken IP core makes Altera FPGAs instantly usable with the variety of SoC, ASSP and ASIC device interfaces in the market,” said Alex Grbic, director of product marketing at Altera. “Demonstrating interoperability with Cavium OCTEON devices shows both the high quality of our Interlaken IP and our commitment to proving out solutions.”
Altera suggests its Interlaken IP core is ideal for multi-terabit routers and switches for access, carrier Ethernet and data center applications that demand IP configurability to optimize for various traffic profiles, and scalability for next-generation platforms. The Interlaken IP includes Altera’s technology-leading transceivers (PMA), PCS, and MAC layers. The PCS layer is hardened within the Stratix V and Arria V FPGAs.
Altera Interlaken IP cores are available now.