VLSI design: Free online UVM training from Aldec
Date: 03/03/2013
VLSI design software company Aldec has launched Fast Track ONLINE, a convenient, online training portal that is available at no cost to the VLSI design verification engineers.
“Engineers from locations around the world, now have access to world-class technical training – at no cost,” said Jerry Kaczynski, Aldec Research Engineer and contributor to the Fast Track™ training curriculum. “These private, online trainings will allow the user to go through each module at their own pace, and even go back to review material. Each individual module also offers a quick self-test to ensure the module is grasped before proceeding.”
This course introduces hardware designers familiar with Design Subset of SystemVerilog into the new world of Universal Verification Methodology (UVM).
Aldec says "Typical hardware designers may not be responsible for maintaining the complete verification suite of large system-level designs, however they often work with verification engineers while creating these environments. For this reason, ‘Fast Track to UVM’ begins with an introduction, or refresher, of SystemVerilog constructs used in UVM (classes, objects, randomization, coverage, interfaces), provides outline of TLM, discusses general structure of UVM and progresses to more a detailed description of verification components and their usage."
This free training portal is available at no cost to all aldec.com registered users.
To get started, visit http://www.aldec.com/en/onlinetraining.
