Date: 24/01/2013

Avago's 28nm chips designed using Cadence Encounter for productivity gain

Cadence Design has announced that Avago Technologies achieved performance of 1GHz, a 57 percent improvement by using Cadence Encounter compared to the previous software. Cadence also claims full-chip implementation turnaround time improved through faster timing closure and fewer design iterations.

“By working with Cadence, we have boosted productivity for our 28-nanometer designs,” said Frank Ostojic, vice president and general manager, ASIC Products Division at Avago. “The EDI System’s new GigaOpt technology enabled improved runtimes, which is critical to hit the market windows for our large designs.”

Cadence says its EDI System provides an effective methodology to optimize power, performance, and area for high-performance, giga-scale designs. In addition, integrated “in-design” signoff capabilities in EDI System ensure correlation between timing and power calculations used during implementation and the final calculations produced by signoff engines, reducing iterations between the implementation and signoff stages, resulting in improved productivity for the design team, as per Cadence.

In Avago’s latest 28-nanometer design, GigaOpt’s “route-driven” optimization, in which the tool takes into account routing layer considerations earlier in the flow, contributed significantly to the improved quality of results obtained during timing optimization, adds Cadence.

“Avago was faced with the challenge of moving a remarkably complex design to market quickly while maintaining the ambitious metrics that ensure high-quality silicon,” said Dr. Chi-Ping Hsu, senior vice president, Research and Development, Silicon Realization Group at Cadence. “The EDI System, with features like the GigaOpt engine, helped Avago meet its power, performance and area requirements for this large-scale project.”
Author: Srinivasa Reddy N