Date: 15/01/2013

VLSI verification tool vendor OneSpin reports double-digit growth in 2012

VLSI chip design automation software vendor OneSpin Solutions has reported double-digit growth in 2012 as adoption of its formal assertion-based verification (ABV) solutions continued for both application specific integrated circuit (ASIC) and field programmable gate array (FPGA) designs.

In addition, co-founders Dr. Raik Brinkmann and Dominik Strasser assumed the roles of president and chief executive officer and vice president of engineering, respectively.

“We consider 2012 to be a year of transformation,” remarks Dr. Brinkmann. “We developed a new business strategy and focused our attention on providing enduring solutions that enable the most thorough and easiest-to-use logic verification software.”

New and efficient design verification solutions from OneSpim includes structural assertion synthesis, system-on-chip (SoC) interconnect verification, coverage closure and ABV intellectual property (IP).
Recently OneSpin secured a round of funding from Azini Capital and is increasing the size of its staff worldwide. OneSpin Solutions provides formal verification solutions for ASIC and FPGA designs to reduce verification effort and costs.
The OneSpin 360 MV Product Family covers areas such as push-button automatic register transfer level (RTL) analysis to OneSpin’s unique GapFreeVerification. OneSpin 360 MV accelerates a multitude of verification tasks, shortens verification schedules and enables engineers to achieve a design quality that cannot be ensured by any other functional verification approach, claims OneSpin.

The OneSpin 360 Equivalence Checker is an automated verification solution to show the functional equivalence of design representations. It can be used standalone for full-chip implementation design equivalence in both ASIC and FPGA flows or in conjunction with the 360 MV Product Family to preserve design quality through subsequent implementation and optimization phases.
Author: Srinivasa Reddy N