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  Date: 12/11/2012

Aldec to present paper related h/w and s/w co-verification at an event on 19th Nov

Aldec, Inc. is presenting a paper on Platform Validation at Verification Futures 2012 in Windsor, United Kingdom, on Monday 19th November; where Platform Validation is at the heart of SoC hardware and software co-verification, and currently one of the EDA industry’s hottest topics.

Jacek Majkowski, Senior Hardware Engineer with Aldec will be presenting the Platform Validation paper and comments: “Whilst embedded system complexity is growing very fast, driven by high customer expectations, verification tools need to keep pace by providing hardware-based methodologies for SoC designers. The complexity grows in both setup of the design under test and the runtime stage of the test. With Aldec’s new HES-7™ platform, setup of the high capacity designs is far simpler with the ability to scale the available capacity of the tool, while Standard Co-Emulation Modeling Interface (SCE-MI) interface provides an efficient and standardized way to test the design on an emulation platform.”

For more details visit www.aldec.com

 
          
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