Altera benchmarks complex Floating-Point DSP designs on 28 nm FPGAs
Altera has announced it has successfully benchmarked complex, high-performance floating-point digital signal processing (DSP) designs on 28 nm FPGA devices. Berkeley Design Technology, Inc. (BDTI) has verified the performance of demanding floating-point DSP applications on Altera’s Stratix V and Arria V 28 nm FPGA development kits. Read BDTI's complete FPGA floating-point DSP analysis at www.altera.com/floatingpoint.
Altera says its floating-point DSP design flow is architected to quickly accommodate design changes with parameterizable interfaces in an environment that includes MATLAB and Simulink from MathWorks, as well as Altera’s DSP Builder Advanced Blockset, enabling FPGA designers to implement and verify complex floating-point algorithms faster than is possible with traditional HDL-based design. The design flow is ideal for designers incorporating high-performance DSP in applications such as radar, wireless base station, industrial automation, instrumentation and medical imaging applications.
“Altera’s floating-point solution enables designers to easily use the massive amounts of high-performance floating-point resources available on an FPGA for DSP data paths,” said Alex Grbic, director, product marketing at Altera. “By benchmarking our solution with BDTI, Altera debunks the myth that FPGAs are limited to high-performance fixed-point processing.”
For this study, BDTI benchmarked matrix equation solvers using Cholesky and QR decomposition. Matrix inversion is representative of the type of processing used in radar systems, multiple-input multiple-output (MIMO) wireless systems, medical imaging and many other DSP applications.
In the evaluation of Altera's floating-point design flow, BDTI stated, "The Altera floating-point design flow simplifies the process of implementing complex floating-point DSP algorithms on an FPGA by streamlining the tools under a single platform.” The report adds, “This integration enables quick development and rapid design space exploration both at the algorithmic level and at the FPGA level, and ultimately reduces overall design effort.”