Rambus tests its memory arch using GLOBALFOUNDRIES 28nm SLP
Rambus has announced test results of its two separate memory architecture-based silicon test chips produced using GLOBALFOUNDRIES' 28-nanometer super low power (28nm-SLP) process. The first test chip tested for mobile memory applications, such as smartphones and tablets. The second test chip for compute main memory applications, such as servers. Rambus says the results of the two test chips have surpassed power and performance expectations.
"The partnership with GLOBALFOUNDRIES is vital to our ongoing commitment to innovation that advances the leading edge of electronics performance," said Sharon Holt, senior vice president and general manager of the Semiconductor Business Group at Rambus. "GLOBALFOUNDRIES' 28nm-SLP process is ideal for achieving multi-gigahertz data rates at unmatched power efficiencies."
"Our 28nm-SLP technology gives SoC designers a robust manufacturing option for a new generation of feature-rich consumer and mobile devices, and assures optimal power consumption that is critical for success in these markets," said Mojy Chian, senior vice president of Design Enablement at GLOBALFOUNDRIES. "We are pleased to be working closely with Rambus to demonstrate the capabilities and design enablement ecosystem available for the industry's most cost-effective and versatile 28SLP process."
Rambus' mobile and server memory architectures are designed for applications such as 3D gaming, HD video streaming, capture and encoding at low power consumption.
GLOBALFOUNDRIES' 28nm-SLP technology is based on bulk silicon CMOS substrates and utilizes the same "Gate First" approach to High-k Metal Gate (HKMG) that has reached volume production in GLOBALFOUNDRIES Fab 1 in Dresden, Germany.
More information on Rambus' design implementation using the GLOBALFOUNDRIES 28nm-SLP process can be found in the companies' 28nm collaboration white paper at: http://globalfoundries.com/eBooks/white%20papers/GF_Rambus_WhitePaper.aspx