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  Date: 18/06/2012

Missed DAC! VLSI designers can read Aldec's presentation through its webinar

Aldec has said the top requests from visitors to Aldec's booth at recently concluded electronics design software focused event DAC included one-on-one Ask Aldec Q&A Sessions where attendees learned more about the latest product updates, roadmaps and demonstrations. UVM, Hardware emulation solutions, simulation on the cloud and VHDL verification methodology were also popular technical session topics.

Those who miss DAC can still read Aldec's top requested Technical Presentations in a convenient webinar format.
Upcoming Webinar Schedule announced by Aldec:

Simulation on the Cloud: Unlimited Possibilities

Thursday, June 28, 2012
11:00am to 12:00pm (PDT) Register

Aldec has enabled running RTL and Timing simulation on the secured cloud, providing access to a virtually unlimited number of high performance servers. Learn about cloud security, benefits and how to set up and run simulation on the cloud.
Register to receive free node hours on Aldec Cloud. Trial offer runs through June 30, 2012.

OS-VVM: High-Level VHDL Verification

Thursday, July 19, 2012
11:00am to 12:00pm (PDT) Register

Standard VHDL has all the features necessary to code randomization of stimulus and functional coverage while verifying larger, system-level designs. Learn how Open Source VHDL Verification Methodology (OS-VVM) makes this easier.


To learn more or register, please visit www.aldec.com/events.

 
          
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