Date: 19th Mar 2012
FPGA-RLDRAM interface is demonstrated
Xilinx, Inc. and Micron Technology, Inc. have demonstrated
an FPGA interfacing with RLDRAM 3 memory, a new and emerging
memory standard for high-end networking applications such
as packet buffering and inspection, linked lists, and lookup
RLDRAM 3 memory uses innovative circuit design to minimize
the time between the beginning of an access cycle and the
instant that the first data is available. Ultra-low bus
turnaround time enables higher sustainable bandwidth with
near-term balanced read-to-write ratios.
"The new RLDRAM 3 interface is ideal for Xilinx and
Micron's mutual customers in the high-end networking space
who require higher speed, higher density, lower power and
lower latency," said Derek Curd, technical marketing
manager at Xilinx. "The RLDRAM 3 hardware demonstration
shows how we're able to achieve a much more efficient transfer
of network data."
A video of the new Virtex-7 FPGA and Micron RLDRAM 3 memory
interface solution from Xilinx and Micron can be viewed
"Xilinx has been a longtime partner of Micron, going
back to the early definition efforts of RLDRAM 3 memory,"
said Robert Feurle, vice president of Micron's DRAM marketing.
"Together, we welcome the ability to demonstrate and
deliver performance advantages of RLDRAM 3 with the latest
Virtex-7 and Kintex-7 families."
Hardware demonstrations of the Xilinx RLDRAM 3 Memory interface
IP core are available now with user configurable IP cores
available in ISE Design Suite 13.4 in September 2012. Qualified
Micron RLDRAM 3 memory devices are available now in x18
and x36 organizations across all speed grades from 800 to
1066MHz. For complete information visit: micron.com/rldram.