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  Date:29th Jan 2012

Altera uses Mentor Graphics Veloce for verifications of its FPGA designs

Altera has adopted the Mentor Graphics Veloce emulator platform for the verification of its FPGA chips.

"The level of integration in leading-edge FPGAs requires that we leverage the most sophisticated emulation and verification tools so that we can achieve our time-to-market goals, performance requirements, and minimize design risks in our latest device portfolio," said David Moore, director, software and IP engineering at Altera. "Using Mentor's Veloce platform lets us quickly and accurately exercise hardware designs at performance levels orders of magnitude higher than that achievable by RTL simulation and enables greatly reduced debug cycles as a result."

The Veloce platform is suggested to peform well for transaction-based verification and traditional in-circuit emulation (ICE).


 
          
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