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  Date: 15th Feb 2011

Panasonic packs precision analog and motion sensor electronics in 2x2 mm chip

Panasonic Corporation has developed 2mmx2mm measuring inertial sensor signal processing IC chip by using 1.8V 110nm BiCMOS semiconductor technology so that surface-area of the high-precision analog circuit is reduced by half.

In order to miniaturize inertial sensor modules, the great challenge has involved the size of the sensor signal processing ICs which, though just a few square millimeters, occupy a large space within the module. Sensor signal processing ICs amplify faint signals outputted from a sensor and convert them to electrical signals depending on the inertial force. Since approximately 80% of the area of such an IC chip is occupied by high-precision analog circuits, it had been considered difficult to reduce the area of the IC through fine process formation.

The sensors themselves have also been miniaturized, causing the level of sensor signals to be reduced. This phenomenon necessitated a reduction in low-frequency noise generated in the first-stage amplifier circuit, which amplifies the sensor signals. However, the noise reduction would then result in an increase in area with conventional CMOS analog circuits. Furthermore, recent industry demands have focused on the high functionality of sensor modules, such as built-in AD converters and multi-axes, which again results in an increase in area for the sensor signal processing ICs.

Panasonic says it has resolved these issues by using advanced semiconductor processing technology.
The features of this device as listed by Panasonic are:

1. The world's smallest chip size: reduced to 40% of the conventional chip area (300nm process)
Low-frequency noise (1/f noise) generated in the first-stage amplifier: reduced to 1/10 of that of conventional amplifiers - allowing the sensor sensitivity to be improved and therefore compensating for the reduction in output signal caused by the miniaturization of the sensor.
2. Built-in AD converters: easy connection to the latter-stage LSIs and more flexible design, using digital rather than analog output signals.


3. The first-stage amplifier of this device has been designed using the industry's smallest bi-polar transistors, using DTIs molded in a 110nm process. The advantage of bi-polar transistors is that low-frequency noise generated by the transistors themselves is approximately 1/100 the level generated by the conventional CMOS analog circuits.
4. Newly developed, small-sized delta-sigma AD converters operating at 1.8V, with a signal power/noise power (S/N) ratio reaching 99dB.

 
          
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