Date:23rd Sep 2011
Altera demonstrates floating-point DSP
design flow on an FPGA
Altera Corporation has demonstrated its new floating-point
digital signal processing (DSP) design flow using FPGAs.
Altera claims it is the industry's first model-based floating-point
design tool that allows implementation of complex floating-point
DSP algorithms on an FPGA. Independent analysis conducted
by Berkeley Design Technology, Inc. (BDTI) validates the
high performance, efficiency and ease of implementing floating-point
DSP designs in Altera's Stratix and Arria FPGA families.
The floating-point DSP design flow includes Altera's floating-point
DSP compiler, which is integrated into the DSP Builder Advanced
Blockset, Quartus II RTL tool chain, and ModelSim simulator,
as well as the MATLAB and Simulink tools from MathWorks
to simplify the DSP algorithm-implementation process on
FPGAs. The floating-point design flow combines and integrates
the algorithm modeling and simulation, RTL generation, synthesis,
place and route, and design verification stages. The integration
enables quick development and rapid design-space exploration,
both at the algorithmic level and at the FPGA level, and
ultimately reduces overall design effort, as per Altera.
"Using Altera's high-level DSP model-based flow, designers
can implement and verify complex floating-point algorithms
more efficiently and quickly than would be possible with
traditional HDL-based design," said Vince Hu, vice
president of product and corporate marketing at Altera.
"Once the algorithm is modeled and debugged at a high
level, the design can be easily synthesized and targeted
to any Altera FPGA."
Altera says its new design flow is suitable to the demanding
linear algebra problems typically requiring the dynamic
range offered by floating-point DSP, BDTI benchmarked a
parameterizable floating-point matrix-inversion design.
Matrix inversion is representative of the type of processing
used in radar systems, multiple-input, multiple output (MIMO)
wireless systems, medical imaging and many other DSP applications.
In the evaluation of Altera's floating-point design flow,
independent technology analysis firm BDTI stated, "Rather
than building a datapath consisting of elementary floating-point
operators, the floating-point compiler generates a fused
datapath that combines elementary operators into a single
function or datapath. In doing so, it eliminates the redundancies
present in traditional floating-point FPGA designs."
BDTI concluded, "With the fused datapath methodology,
complex floating-point datapaths are implemented with higher
performance and efficiency than previously possible."