Electronics Engineering Herald                  National Semiconductor power ICs
Home | News | New Products | India Specific | Design Guide | Sourcing database | Student Section | About us | Contact us | What's New

News

  Date:19th Sep 2011

Reference design for delivering advanced communication services over low-cost packet n/ws

Vitesse Semiconductor Corporation and Zarlink Semiconductor has announced availability of a joint reference design that delivers synchronization required by carriers to deliver scalable, higher bandwidth communication services over packet-based networks.

The reference design combines Vitesse's VSC8574 Gigabit Ethernet (GE) PHY transceiver and Zarlink's ZL30143 Synchronous Ethernet (SyncE) dual channel system synchronizer. The Vitesse PHY provides both primary and secondary recovered clock outputs as clock references to Zarlink's ZL30143 in the synchronous timing system to provide a low jitter Synchronous Ethernet solution. The reference design meets the performance demands for timing synchronization in accordance with ITU-T Recommendation G.8262 for wireless base stations, radio network controllers, gateways, aggregation and transmission equipment, and routers while reducing design complexity. For applications requiring IEEE 1588v2 phase and time synchronization, Vitesse's VSC8574 device provides both one-step and two-step time stamping in the physical layer with +/-10ns or better accuracy and can be complemented with Zarlink's ZL3034x family of IEEE 1588v2-enabled timing products.

"Packet-based Ethernet technologies enable carriers to cost-effectively scale bandwidth to meet the demands of new mobile multimedia applications," said Jamileh Davoudi, product marketing manager with Zarlink's Timing and Synchronization product line. "Vitesse and Zarlink have combined our Synchronous Ethernet timing expertise to provide manufacturers with an easy-to-implement solution to support multiple services over a single network. In addition, this reference design allows the flexibility to upgrade designs to IEEE 1588v2 for wireless technologies, such as WCDMA-TDD, CDMA2000 and Mobile WiMAX."

"Our reference design with Zarlink gives equipment manufacturers and service providers a seamless upgrade path to integrate precise timing features required to deliver advanced communication services over lower-cost packet networks," said Brian Jaroszewski, senior product manager at Vitesse. "Complemented by our broad Carrier Ethernet portfolio of GE, 10GE and OTN PHY devices with physical layer IEEE 1588v2 support, Vitesse offers full network synchronization support sufficient for WiMAX and LTE backhaul, as well as other timing critical applications."

Reference Design Details
The reference design, known as the VSC8574EV, is available immediately. Additional details about the VSC8574EV are available at www.vitesse.com/ce/1588-ref-design. Contact your local Vitesse sales office to learn more.

Specific devices on the VSC8574EV include:
Zarlink's ZL30143 SyncE dual channel device is a family member of footprint-compatible devices offering the full range of features required for timing and synchronization across packet networks. Visit www.zarlink.com/timing_PacketNetworks.htm for more product details.

Vitesse's VSC8574 quad port Gigabit PHY is part of its energy-efficient SimpliPHY family of Gigabit Ethernet (GE) physical layer devices. Visit www.vitesse.com/products/product.php?number=VSC8574 for more information.


 
          
Xilinx 7 series FPGA
Home | News | New Products | India Specific | Design Guide | Sourcing database | Student Section | About us | Contact us | What's New
©2010 Electronics Engineering Herald