Date: 11th Aug 2010

Synopsys Galaxy Implementation Platform Used by TSMC for 28nm Process

Synopsys has annonuced TSMC has successfully taped out a complex 28-nanometer (nm) Product Qualification Vehicle (PQV) test chip using Synopsys' Galaxy Implementation Platform. Key features used to design the PQV test chip include 28-nm design rule support for place-and-route, interconnect process modeling, IEEE 1801-2009 (UPF)-based hierarchical low power flow, power-aware design-for-test (DFT) and advanced signoff capabilities. Synopsys tools exercised by TSMC in the RTL-to-GDSII implementation and signoff flow for this test chip development included DC Ultra RTL synthesis, IC Compiler physical implementation, PrimeTime SI timing signoff and StarRC Ultra parasitic extraction.

"We continuously work with Synopsys to identify EDA and manufacturing solutions that address the challenges of the latest advanced semiconductor processes," said ST Juang, senior director of design infrastructure marketing at TSMC. "As a result of our PQV test chip design project, we have successfully used Synopsys' Galaxy Implementation Platform in our 28-nanometer process, including capabilities for hierarchical low power implementation, routing rules and manufacturing compliance. We appreciate Synopsys' on-going collaboration during our aggressive process development and deployment projects that allow us to deploy our solutions to our common customers in a very timely manner."

On the same subject Magma had very recently announced that TSMC has used Magma's Quartz DRC for physical verification for its 28-nanometer (nm) product qualification vehicle (PQV) test chip.

PQV consists of VLSI combo chips such as logic, memory and ASIC samples representing design data of fab customers, which is going to be used in production designs.