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   Date: 15th June 2010

New technology for Si nanowire transistors improves on-state current level by 75%

Toshiba has announced that it has developed a technology for a nanowire transistor, a major candidate for a 3D structure transistor for system LSI in the 16nm generation and beyond. The company has achieved a 1mA/µm on-current by reducing parasitic resistance thus improving the on-current level by 75%. It will be presented at the 2010 Symposium on VLSI Technology in Hawaii, on June 17.

As the size of current planar transistors reduces the current leakage between the source and the drain at its off-stage (off-leakage) becomes one critical problem that can affect circuit reliability. To overcome this, transistors with a 3D structure, including silicon nanowire transistors, are being investigated. The silicon nanowire transistor consists thin wire-shaped silicon channel (nanowire channel) that is effectively controlled by the surrounding gate this aids in suppressing off-leakage and achieve further short-channel operation. The parasitic resistance in the nanowire-shaped source/drain, especially in the region under the gate sidewall, degrades the on-current. Toshiba says that it has overcome this problem by optimizing gate fabrication and reducing the thickness of the gate sidewall, from 30nm to 10nm. Low parasitic resistance was realized by epitaxial silicon growth on the source/drain with a thin gate sidewall, which leads to a 40% increase in on-current. They have also achieved a further 25% increase in current performance by changing the direction of the silicon nanowire channel from the <110> to <100> plane direction. Utilizing these technologies, Toshiba has achieved an on-current level of 1mA/µm, when the off-current is 100nA/µm i.e. a 75% increase in the on-current at the same off-current condition.

          
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