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   Date: 31st Oct 09

Cadence low power design flow for SMIC 65nm process

Cadence has announced that it has delivered a low-power design flow targeting the 65-nanometer process at SMIC, where the flow enables fast design of low-power semiconductors using a single design platform.

The SMIC 65-nm low-power Reference Flow 4.0 includes the Cadence low-power solution, with Encounter conformal low power, Incisive enterprise simulator, Encounter RTL compiler, Encounter digital implementation system, Cadence QRC extraction, Encounter timing system and power system.

Validation of the flow was accomplished through implementation of low-power chips utilizing SMIC's 65-nm libraries, including effective current source model (ECSM) standard cells, power management cells, PLLs, SRAMs and I/O libraries. Low-power technologies employed in the design include power gating and multi-supply/multi-voltage (MSMV) techniques to reduce leakage and dynamic power consumption.

"Power is now a critical design constraint, as important as timing and area from both a technology and cost standpoint," said Max Liu, vice president of the Design Services Center at SMIC. "The SMIC-Cadence Reference Flow 4.0 addresses the need for power-efficient design innovation with an advanced, automated low-power design capability."

"Power efficiency is a key requirement for many new semiconductors, yet designers sometimes think it's too new and therefore too risky," said Steve Carlson, vice president of product marketing at Cadence. "The Cadence Low-Power Solution provides a complete, silicon-validated front-to-back flow for designers targeting SMIC's 65-nanometer process technology, including functional and structural verification, while increasing productivity. It's fast, easy and proven."

          
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