Electronics Engineering Herald                 
Home | News | New Products | India Specific | Design Guide | Sourcing database | Student Section | About us | Contact us | What's New
Processor / MCU / DSP
Memory
Analog
Logic and Interface
PLD / FPGA
Power-supply and Industrial ICs
Automotive ICs
Cellphone ICs
Consumer ICs
Computer ICs
Communication ICs (Data & Analog)
RF / Microwave
Subsystems / Boards
Reference Design
Software / Development kits
Test and Measurement
Discrete
Opto
Passives
Interconnect
Sensors
Batteries
Others

New Products

  Date: 18/10/2016

DUSB2-ULPI IP for hardware implementation of full/high-speed peripheral controller

If you are looking to do a hardware implementation of full/high-speed peripheral controller on your SoC chip, the new USB2.0 IP from Digital Core Design can be a option. Basically the new DUSB2-ULPI IP contains USB PID and address recognition logic, state machines which can handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic.

DUSB2-ULPI IP supports USB 2.0 speeds and not the USB 3.0. The company says, USB 2.0 is still relevant as 99.9% of embedded system applications are still dependent on USB 2.0

As of now, this USB2.0 user can be benefited from this. This IP supports irrespective of any process you are using. Digital Core design says, this new IP strictly conforms to USB specification version2 and ULPI version 2 and it is also delivered with fully automatic test bench and complete set of tests basically allowing you easy package validation at each stage of SoC design.

To tell you some of the features available in this IP, this supports a full speed operation of 12Mbp and also High-speed operation of480 Mbps. The software is configurable EP0 control endpoint size of 8- 64 bytes.

The other features as listed by the company are mentioned below:
SOFTWARE configurable 15 IN/OUT endpoints:
Configurable number of endpoints
Configurable type of each endpoint: INTERRUPT, BULK or ISOCHRONOUS
Configurable direction of each endpoint
Configurable size of each endpoint: 8-1024 bytes
Supports ULPI Transceiver Macro cell Interface
Synchronous RAM interface for FIFOs
Suspend and resume power management functions
Simple interface allows easy connection to the 8-, 16-, 32-bit CPUs
Allows operation from a wide range of CPU clock frequencies
Fully synthesizable
Static synchronous design
Positive edge clocking
No internal tri-states
Scan test ready

 
          
ADVT
Home | News | New Products | India Specific | Design Guide | Sourcing database | Student Section | About us | Contact us | What's New
©2012 Electronics Engineering Herald