Lam Research's etch tech pushing 3D semiconductor memory production
Date: 16/05/2015
Lam Research claims its Kiyo F Series conductor etch system is enabling volume production of 3D NAND flash and advanced DRAM by memory semiconductor manufacturers.
Lam's technology helps in achieving tight critical dimension (CD) uniformity and control for 3D NAND and uniform etch depth for DRAM. The technology called Mixed-Mode Pulsing (MMP) is behind this achievement.
"For 3D NAND, our customers face significant challenges in addressing difficult etch requirements, meeting aggressive production ramps, and achieving the cost benefits they need to make the transition from planar NAND," said Vahid Vahedi, group vice president, Etch Product Group. "We are collaborating closely with them to address these new challenges and to enable this inflection by delivering robust, timely solutions without compromising productivity."
The term staircase comes into the usage once the single floor planar memory becomes multi dimensional otherwise multi-storey structure. Just like the multi-storey buildings need staircase the multi-storey memory chips also require staircase like electrical connection which need to be etched vertically. Maintaining uniformity of creating such staircases of connections without any variance in electrical properties for volume production of 3-D memory is essential. The critical part of building vertical channels is high aspect ratio (HAR) mask open. Mask open is said to be crucial since it defines the CD and CD uniformity for subsequent etching of the vertical transistor channels.
"For staircase etch, equal-width "steps" are created at the edge of each dielectric-film pair throughout the 3D stack to form a staircase-shaped structure. Because of extensive repetition of these steps during device processing, etching at high throughput with stringent process control is vital. CD variability must be tightly managed since wordline contacts may otherwise miss landing on a step that is too narrow or uneven. For advanced DRAM devices, depth control is a key parameter, particularly for HAR front-end-of-line silicon etch applications. Concerns include aspect ratio loading, where etch rates vary because of differences in feature dimensions, and depth loading, where different etch depths may occur due to pattern density variations." explains Lam on the issues facing manufacturing multi-storey memory monolithic chip and the solutions offered by Lam.
Lam's MMP technology supports atomic layer etching so that higher trim rate for 3D NAND staircase etch can be achieved with good repeatability. Lam's symmetric chamber design and radial tuning helps in achieving uniformity and minimising variance.
Though it has not named any particular semiconductor memory manufacturer, Lam claims all the major memory manufacturers are using Kiyo F Series for critical conductor etch applications.
