1st specs on Hybrid Memory Cube agreed
Date: 02/04/2013
The members of the Hybrid Memory Cube Consortium (HMCC) have reached consensus for the global standard for HMC. HMC packs processor-logic and memory dies one above the other, and connect them through TSV. The members of the consortium members are collaborating to achieve agreement on the next generation of HMC interface standards. HMC benefits the user with some of the Moore's Law-like advantages, such as space saving and increased speed and performance.
"The consensus we have among major memory companies and many others in the industry will contribute significantly to the launch of this promising technology," said Jim Elliott, Vice President, Memory Planning and Product Marketing, Samsung Semiconductor, Inc. "As a result of the work of the HMCC, IT system designers and manufacturers will be able to get new green memory solutions that outperform other memory options offered today."
"This milestone marks the tearing down of the memory wall," said Robert Feurle, Micron's Vice President for DRAM Marketing. "The industry agreement is going to help drive the fastest possible adoption of HMC technology, resulting in what we believe will be radical improvements to computing systems and, ultimately, consumer applications."
"HMC is a very special offering currently on the radar," said JH Oh, Vice President, DRAM Product Planning and Enabling Group, SK hynix Inc. "HMC brings a new level of capability to memory that provides exponential performance and efficiency gains that will redefine the future of memory."
As envisioned, HMC capabilities will leap beyond current and near-term memory architectures in the areas of performance, packaging and power efficiency.
The HMC standard set to break the challenge of "memory wall", a term used for limitation in bandwidth in present memory modules.
The newly agreed HMC specification covers short-reach (SR) and ultra short-reach (USR) interconnection across physical layers (PHYs) for applications requiring tightly coupled or close-proximity memory support for FPGAs, ASICs and ASSPs, such as high-performance networking, and test and measurement. The next goal for the consortium is to further advance standards designed to increase data rate speeds from 10, 12.5 and 15 gigabits per second (Gb/s) up to 28 Gb/s for SR and from 10 Gb/s up to 15 Gb/s for USR.
Some of the members of HMC includes Altera, ARM, Cray, Fujitsu, GLOBALFOUNDRIES, HP, IBM, Marvell, Micron Technology, National Instruments, Open-Silicon, Samsung, SK hynix, ST Microelectronics, Teradyne and Xilinx.
For more details visit www.hybridmemorycube.org.
