VLSI design tool identifies critical issues in RTL phase of ASIC and FPGA designs

Aldec has released VLSI design tool ALINT 2012.12, a static design analysis and checking tool to identify critical issues early in the RTL design phase of ASIC and FPGA designs. ALINT 2012.12 features a team-based task management utility, and a new premium rule library that includes checkers to optimize routing resources in designs targeting today’s largest FPGAs.

“Although each device family is unique as a place and route target, mismanagement of routing resources negatively impacts resource utilization, performance and power,” said Dmitry Melnik, Product Manager, Aldec Software Division. “Within the RTL, routing-unaware design styles limit choices for the place and route tools later in the design cycle. This results in additional routing capacitance and delay, and consequently increased power and impaired performance. In contrast, routing-aware design techniques improve routing utilization and allow place and route applications to consume less of the target device and produce better quality results.”

Core Areas Covered by New Rule Library

Three core issue types addressed by the new checkers implemented in ALINT 2012.12 premium rule library are:

1. Logic placement at different levels of design hierarchy (hierarchical design)

2. Suboptimal cross-hierarchy interconnections that increase fanout

3. I/O port registering issues

The guidelines supported in ALINT’s premium rule library enable logic synthesis and place and route tools to provide more efficient chip utilization. The new rules benefit not only FPGA designs but are also equally applicable to ASIC designs that use multiple FPGA boards for prototyping, where partitioning and resource management can be very challenging.

ALINT 2012.12 Availability: Available now with premium rule plug-in for FPGA routing resources optimization as an add-on option.