Date: 8th July 2011
Simulink Design Verifier 2.0 with automated
error detection and test generation feature
MathWorks has enhanced its Simulink Design Verifier 2.0
with Polyspace analysis technology for automated error detection
and test generation to reduce the time required to find
and fix the root cause of design errors in Simulink models
and decreases the overall cost of verification and validation.
According to Mathworks design engineers in the aerospace,
automotive, medical, and industrial automation and machinery
industries are applying Model-Based Design with formal analysis
methods provided by Simulink Design Verifier 2.0 to identify
design errors in Simulink and Stateflow models without extensive
testing or simulation.
Key features of the product include:
Detection of dead logic, integer and fixed-point overflows,
division by zero, and assertion violation
Blocks and functions for modeling functional and safety
requirements
Test vector generation from functional requirements and
model coverage objectives
Property proving, with generation of violation examples
for analysis and debugging
Fixed-point and floating-point model support
Availabile: Now.
Price: $8000
For more information visit: mathworks.com/products/sldesignverifier.
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