Mentor is providing DRC and LVS tools to make 3D-ICs

In close partnership with Tezzaron Semiconductor and MOSIS, Mentor Graphics Corporation has announced that it is providing DRC and LVS tools that support 3D-IC physical verification to 3D-IC developers. 3D-IC fabrication involves using tens of millions of through silicon vias (TSVs) with dimensions as small as 1.2 x 6 microns and a pitch of 2.4 microns, producing up to 300,000 vertical interconnects per square millimeter.

"Our collaboration allows firms to explore practical applications of true 3D-IC integration in a way that reduces risk and cost, while taking advantage of over a decade of experience in manufacturing 3D-ICs with high density TSVs," said Robert Patti, CTO of Tezzaron Semiconductor.

"Adding Tezzaron's offering to our Multi Project Wafer (MPW) services allows companies to test out 3D-IC concepts using the same provider and model they currently use for their standard semiconductors," said Wes Hansford, director at MOSIS. "By coordinating resources and schedules, we can significantly reduce the effort and risk involved in getting the silicon-proven data required to make effective product roadmap decisions."

"We're working with Tezzaron and MOSIS to ensure that even at the prototype stage our customers will be able to access production-certified Calibre solutions to verify that their 3D-IC designs are manufacturable," said Joseph Sawicki, vice president and general manager of the Design-to-Silicon Division at Mentor Graphics. "The Calibre solution uses foundry-certified PDKs from MOSIS wafer suppliers with extensions for MOSIS-Tezzaron 3D-IC designs."

MOSIS 3D-ICs services include reticle creation, fab reservations, final packaging and testing, and other logistics. Tezzaron's services include backend-manufacturing steps including wafer thinning, backside metal and wafer bonding.