Low power VLSI chip design: Circuit
Introduction: During the desktop PC design era VLSI
design efforts have focused primarily on optimizing speed
to realize computationally intensive real-time functions
such as video compression, gaming, graphics etc. As a result,
we have semiconductor ICs that successfully integrated various
complex signal processing modules and graphical processing
units to meet our computation and entertainment demands.
While these solutions have addressed the real-time problem,
they have not addressed the increasing demand for portable
operation, where mobile phone need to pack all this without
consuming much power. The strict limitation on power dissipation
in portable electronics applications such as smart phones
and tablet computers must be met by the VLSI chip designer
while still meeting the computational requirements. While
wireless devices are rapidly making their way to the consumer
electronics market, a key design constraint for portable
operation namely the total power consumption of the device
must be addressed. Reducing the total power consumption
in such systems is important since it is desirable to maximize
the run time with minimum requirements on size, battery
life and weight allocated to batteries. So the most important
factor to cosider while designing SoC for portable devices
is 'low power design'.
Is Power Really A Problem?
Scaling of technology node increases power-density more than expected.
CMOS technology beyond 65nm node represents a real challenge
for any sort of voltage and frequency scaling Starting from
120nm node, each new process has inherently higher dynamic
and leakage current density with minimal improvement in
speed. Between 90nm to 65nm the dynamic power dissipation
is almost same whereas there is ~5% higher leakage/mm2.Low
cost always continues to drive higher levels of integration,
whereas low cost technological breakthroughs to keep power
under control are getting very scarce.
Modern System-on-Chip demand for more power. In both logic
and memory, Static power is growing really fast and Dynamic
power kind of grows. Overall power is dramatically increasing.
If the semiconductor integration continue to follow Moore's
Law, the power density inside the chips will reach far higher
than the rocket nozzle.
Do We Need To Bother With Power?
Power dissipation is the main constrain when it comes to
Portability. The mobile device consumer demands more features
and extended battery life at a lower cost. About 70% of
users demand longer talk and stand-by time as primary mobile
phone feature. Top 3G requirement for operators is power
efficiency. Customers want smaller & sleeker mobile
devices. This requires high levels of Silicon integration
in advanced processes, but advanced processes have inherently
higher leakage current. So there is a need to bother more
on reducing leakage curret to reduce power consumption.
Why Power Matters in SOC?
Power Management matter in System on Chip due to following
a)Packaging and Cooling costs.
b)Digital noise immunity,
c)Battery life (in portable systems)
Sources of Power Dissipation:
The power dissipation in circuit can be classified into
three categories as described below.
Dynamic power consumption: Due to logic transitions
causing logic gates to charge/discharge load capacitance.
Short-circuit current: In a CMOS logic P-branch and
N-branch are momentarily shorted as logic gate changes state
resulting in short circuit power dissipation.
Leakage current: This is the power dissipation that
occurs when the system is in standby mode or not powered.
There are many sources of leakage current in MOSFET. Diode
leakages around transistors and n-wells, Subthreshold Leakage,
Gate Leakage, Tunnel Currents etc. Increasing 20 times for
each new fabrication technology. Went from insignificant
to a dominating factor.
Low-Power Design Techniques:
An integrated low power methodology requires optimization
at all design abstraction layers as mentioned below.
1. System: Partitioning, Power down
2. Algorithm: Complexity, Concurrency, Regularity
3. Architecture: Parallelism, Pipelining, Redundancy, Data
4. Circuit Logic: Logic Styles, Energy Recovery, Transistor
5. Technology: Threshold Reduction, Multithreshold Devices.
Dynamic power varies as VDD2. So reducing the supply voltage
reduces power dissipation. Also selective frequency reduction
technique can be used to reduce dynamic power. Multi threshold
voltage can be used to reduce leakage power at system level.
Transistor resizing can be used to speed-up circuit and
reduce power. Sleep transistors which we will discuss in
following tutorials can be used effectively to reduce standby
power. Parallelism and pipelining in system architecture
can reduce power significantly. Clock disabling, power-down
of selected logic blocks, adiabatic computing, software
redesign to lower power dissipation are the other techniques
commonly used for low power design.
VLSI circuit design for low power:
The growing market of portable (e.g., cellular phones,
gaming consoles, etc.), battery-powered electronic systems
demands microelectronic circuits design with ultra low power
dissipation. As the integration, size, and complexity of
the chips continue to increase, the difficulty in providing
adequate cooling might either add significant cost or limit
the functionality of the computing systems which make use
of those integrated circuits. As the technology node scales
down to 65nm there is not much increase in dynamic power
dissipation. However the static or leakage power is same
as or exceeds the dynamic power beyond 65nm technology node.
Hence the techniques to reduce power dissipation is not
limited to dynamic power. In this article we discuss circuit
and logic design approaches to minimize Dynamic, Leakage
and Short Circuit power dissipation. Power optimization
in a processor can be achieved at various abstract levels
have a large potential for power saving even these techniques
tend to saturate as we integrate more functionality on an
IC. So optimization at Circuit and Technology level is also
very important for miniaturization of ICs.
Total Power dissipated in a CMOS circuit is sum total of
dynamic power,short circuit power and static or leakage
power. Design for low-power implies the ability to reduce
all three components of power consumption in CMOS circuits
during the development of a low power electronic product.
In the sections to follow we summerize the most widely used
circuit techniques to reduce each of these components of
power in a standard CMOS design.
Figure 3.Components of Power in CMOS circuit
Ptotal = CLVDD2 + tscVDDIpeak + VDDIleakage
Dynamic Power Suppression
Dynamic/Switching power is due to charging and discharging
of load capacitors driven by the circuit. Supply voltage
scaling has been the most adopted approach to power optimization,
since it normally yields considerable power savings due
to the quadratic dependence of switching/dynamic power PSwitching
on supply voltage VDD. However lowering the supply voltage
affects circuit speed which is the major short-coming of
this approach. So both design and technological solutions
must be applied to compensate the decrease in circuit performance
introduced by reduced voltage. Some of the techniques often
used to reduce dynamic power are described below.
In adiabatic circuits instead of dissipating the power
is reused. By externally controlling the length and shape
of signal transitions energy spent to flip a bit can be
reduced to very small values. Since diodes are thermodynamically
irreversible they are not used in the design of Adiabatic
Logic. MOSFETs should not be turned ON when there is significant
potential difference between source and drain. And should
not be turnoff when there is a significant current flowing
through the device.
Figure 4.Charge Recovery Logic
In the adiabatic circuit shown above initially, f and /f
at Vdd/2, P at Gnd, and /P at Vdd. On valid input, the pass
gate is turned on by gradually swinging P and /P. Rails
f and /f "split", gradually swinging to Vdd and
Gnd. As soon as output is sampled, pass gate is turned off.
Internal node is restored by gradually swinging f and /f
back to Vdd/2.Once the device is on energy transfer takes
place in a controlled manner so that there is no potential
drop across the device.
Logic Design for Low Power
Choices between static versus dynamic topologies, conventional
CMOS versus pass-transistor logic styles and synchronous
versus asynchronous timing styles have to be made during
the design of a circuit. In static CMOS circuits, the component
of power due to short circuit current is about the 10% of
the total power consumption. However, in dynamic circuits
we don't come across this problem, since there is no any
direct dc path from supply voltage to ground. Only in domino-logic
circuits there is such a path, in order to reduce sharing,
hence there is a small amount of short-circuit power dissipation.
Figure 5.(a) Static NOR and
Figure 5.(b) Dynamic NOR circuits
Similarly we can use pass transsitor logic to exploit reduced
swing to lower power (e.g., reduced bit-line swing in memory).
Figure 6.Pass Transistor Logic
P = CL* Vdd* (Vdd-Vt)
Glitches occur in a logic chain when two parallel driving
common gate arrive at different times. The output momentarily
switches to incorrect value before settling to correct result.
Consider circuit shown below. Let us assume that in the
absence of buffer path A is high speed and Path B is slow.
Initially if A=0 and B=1 then Z=0.Next if B is to switch
to 0 and A to 1 since B is slow the data 0 arriving at B
will be slow and hence Z switches towards 1 momentarily
before switching back to 0 resulting in power dissipation.
Figure.7 Glitch Free AND Gate
As shown in figure above buffers are generally used to delay
path A to overcome glitches
Logic Level Power Optimization
During logic optimization for low power, technology parameters
such as supply voltage are fixed, and the degrees of freedom
are in selecting the functionality and sizing the gates.
Path equalization with buffer insertion is one of the techniques
which ensures that signal propagation from inputs to outputs
of a logic network follows paths of similar length to overcome
glitches. When paths are equalized, most gates have aligned
transitions at their inputs, thereby minimizing spurious
switching activity/glitches (which is created by misaligned
Figure.8 Logic Remapping for Low Power
(T. Burdet et.al, , Journal of VLSI Signal Processing Systems,
vol.13, no. 2-3, pp. 203-221, August 1996)
Other logic-level power minimization techniques include
local transformations as shown in figure above. A re-mapping
transformation is shown, where a high-activity node (marked
with x) is removed and replaced by new mapping onto an and
Standby Mode Leakage Suppression
Static/Leakage power, originates from substrate currents
and subthreshold leakages. For technologies 1 µm and
above , PSwitching was predominant. However for deep-submicron
processes below 180nm, PLeakage becomes dominant factor.
Leakage power is a major concern in recent technologies,
as it impacts battery lifetime. CMOS technology has been
extremely power-efficient when transistors are not switching
or in stand-by mode, and system designers expect low leakage
from CMOS chips. To meet leakage power constraints, multiple-threshold
and variable threshold circuit techniques are often used.
In multiple-threshold CMOS, the process provides two different
threshold transitors. Low-threshold are employed on speed-critical
sub-circuits and ther are fast and leaky. High-threshold
transistors are slower but exhibit low sub-threshold leakage,
and they are employed in noncritical/slow paths of the chip.
As more transistors become timing-critical multiple-threshold
techniques tend to lose effectiveness.
Variable Body Biasing:
Variable-threshold circuits dynamically control the threshold
voltage of transistors through substrate biasing and hence
overcome shortcoming associated with multi-threshold design.
When a variable-threshold circuit is in standby, the substrate
of NMOS transistors is negatively biased, and their threshold
increases because of the body-bias effect. Similarly the
substrate of PMOS transistors is biased by positive body
bias to increase their Vt in stand-by. Variable-threshold
circuits can, in principle, solve the quiescent/static leakage
problem, but they require control circuits that modulate
substrate voltage in stand-by. Fast and accurate body-bias
control with control circuit is quite challenging, and requires
carefully designed closed-loop control. When the circuit
is in standby mode the bulk/body of both PMOS and NMOS are
biased by third supply voltage to increase the Vt of the
MOSFET as shown in the Figure. However during normal operation
they are switched back to reduce the Vt.
Figure .9 Variable Body Biasing
Sleep Transistors are High Vt transistors connected in
series with low Vt logic as shown below .When the main circuit
consisting of Low Vt devices are ON the sleep transistors
are also ON resulting in normal operation of the circuit.
When the circuit is in Standby mode even High Vt transistors
are OFF. Since High Vt devices appear in series with Low
Vt circuit the leakage current is determined by High Vt
devices and is very low. So the net static power dissipation
Figure.10 Circuit Design with Sleep Transistors
Dynamic Threshold MOS:
In dynamic threshold CMOS (DTMOS), the threshold voltage
is altered dynamically to suit the operating state of the
circuit. A high threshold voltage in the standby mode gives
low leakage current, while a low threshold voltage allows
for higher current drives in the active mode of operation.
Dynamic threshold CMOS can be achieved by tying the gate
and body together. The supply voltage of DTMOS is limited
by the diode built-in potential in bulk silicon technology.
The pn diode between source and body should be reverse biased.
Hence, this technique is only suitable for ultralow voltage
(0.6V and below) circuits in bulk CMOS.
Figure .11 DTMOS Circuit
Short Circuit Power Suppression
Short-circuit power, is caused by the short circuit currents
that arise when pairs of PMOS/NMOS transistors are conducting
simultaneously. In static CMOS circuits, short-circuit path
exists for direct current flow from VDD to ground, when
VTn< Vin< VDD-|VTp|
Figure .12 Short Circuit Power in CMOS Circuits
One way to reduce short circuit power is to keep the input
and output rise/fall times the same. If Vdd < Vtn + |Vtp|
then short-circuit power can be eliminated. If the load
capacitance is very large, the output fall time is larger
than the input rise time. The drain-source voltage of the
PMOS transistor is 0.Hence the short-circuit power will
be 0. If the load capacitance is very small,the output fall
time is smaller than the input rise time. The drain-source
voltage of the PMOS transistor is close to VDD during most
of the transition period. Hence the short-circuit power
will be very large.